library IEEE;
use IEEE.std_logic_1164.all;

entity decoder is
   port(clk: in std_logic;
        rst: in std_logic;
        D_I: in std_logic;
        D_O: out std_logic);
end decoder;

architecture beh of decoder is
   type miller_states is (s1, s2, s3, s4);
   signal state: miller_states := s1;
   signal clk6: std_logic:='1';
   signal clk24: std_logic:='1';
   signal var: std_logic:='0';
   signal count_out: std_logic:='0';
   
begin
   process(clk)
       variable count : integer := 1;
   begin
       if (count<=3 and clk'event and clk='1') then
          clk6<='1'; count:=count+1;
       elsif (count>3 and count<=6 and clk'event and clk='1') then
          clk6<='0'; count:=count+1;
       end if;
       
       if (count=7) then
         count:=1;
       end if;
   end process;
        
   process(clk, D_I, rst)
       variable count : integer := 1;
       variable count_data : integer := 1;
   begin
      -- if (count_data<4 and D_I'event and D_I='0') then
       --   count_data:=count_data+1;
      -- end if; 
    
       
       if (rst='0') then
       if (count<=12 and clk'event and clk='1') then
          clk24<='1'; count:=count+1;
       elsif (count>12 and count<=24 and clk'event and clk='1') then
          clk24<='0'; count:=count+1;
       end if;
       end if;
       
       if (count=25) then
         count:=1;
       end if;
       if (rst='1') then
          count_data:=0;
       end if;
   end process;
   
   process(D_I, clk24)
   begin
        case state is
        when s1=>
            if((D_I='0' and clk24'event and clk24='1')) then
                state<=s4; var<='0';
            elsif(D_I='1' and clk24'event and clk24='1') then
                state<=s2; var<='1';
            end if;
               
        when s2=>
            if(D_I='0' and clk24'event and clk24='1') then
                state<=s4; var<='1';
            elsif((D_I='1' and clk24'event and clk24='1')) then
                state<=s3; var<='0';
            end if;
         
        when s3=>
            if(D_I='0' and clk24'event and clk24='1') then
                state<=s1; var<='1';
            elsif((D_I='1' and clk24'event and clk24='1')) then
                state<=s2; var<='0';
            end if;
    
        when s4=>
            if((D_I='0' and clk24'event and clk24='1')) then
                state<=s1; var<='0';
            elsif(D_I='1' and clk24'event and clk24='1') then
                state<=s3; var<='1';
            end if; 
        
        end case;
   end process;
       
   process(clk24)
      variable count : integer := 1;
   begin
       if(rst='0') then
          if(count_out='1' and clk24'event and clk24='1') then
               D_O<=var;
          end if;
           
          if(clk24'event and clk24 = '1') then
               if(count_out = '1') then
                  count_out<='0';
               else
                  count_out<='1';
               end if;
          end if; 
      else
         D_O<='0';
      end if;
   end process;
   
end architecture beh;